A repository of stochastic arithmetic units for reproducible research.
Ardalan Najafi, Moritz Weissbrich, Guillermo Paya Vaya and Alberto Garcia-Ortiz A Fair Comparison of Adders in Stochastic Regime 2017 27th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) PDF Bibtex
@INPROCEEDINGS{8106990, author={A. {Najafi} and M. {Weissbrich} and G. {Paya-Vaya} and A. {Garcia-Ortiz}}, booktitle={2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)}, title={A fair comparison of adders in stochastic regime}, year={2017}, volume={}, number={}, pages={1-6}, keywords={adders;logic design;low-power electronics;stochastic processes;error tolerant adder type II;power-efficient systems;approximate circuits;stochastic techniques;approximate arithmetic units;arithmetic circuits;adders;Adders;Computer architecture;Stochastic processes;Generators;Delays}, doi={10.1109/PATMOS.2017.8106990}, ISSN={}, month={Sep.},}
Ayad Dalloo, Ardalan Najafi, Alberto Garcia-Ortiz Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder IEEE Transactions on Very Large Scale Integration (VLSI) Systems PDF Bibtex
@ARTICLE{8341951, author={A. {Dalloo} and A. {Najafi} and A. {Garcia-Ortiz}}, journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, title={Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder}, year={2018}, volume={26}, number={8}, pages={1595-1599}, keywords={adders;cost reduction;logic design;logic gates;integrated systems;architectural template;hardware cost;systematic design;approximate adder;optimized lower part constant-OR adder;nonsystematic methodology;LOCA;time 10.0 year;word length 8 bit;Adders;Hardware;Logic gates;Computer architecture;Delays;Very large scale integration;Adder architecture;approximate computing;error-cost tradeoff;stochastic computing}, doi={10.1109/TVLSI.2018.2822278}, ISSN={1063-8210}, month={Aug},}
Ardalan Najafi, Moritz Weissbrich, Guillermo Paya Vaya and Alberto Garcia-Ortiz Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics IEEE Journal on Emerging and Selected Topics in Circuits and Systems PDF Bibtex
@ARTICLE{8354693, author={A. {Najafi} and M. {Weissbrich} and G. {Paya-Vaya} and A. {Garcia-Ortiz}}, journal={IEEE Journal on Emerging and Selected Topics in Circuits and Systems}, title={Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics}, year={2018}, volume={8}, number={4}, pages={736-745}, keywords={adders;approximation theory;coherent design;hybrid approximate adders;unified design framework;technology scaling;nonsystematic methodology;robust error metrics;approximate accelerator;ad-hoc methodology;Adders;Error analysis;Systematics;Computer vision;Usability;Approximate adders;error metrics;computer vision;generic template;automatic design framework}, doi={10.1109/JETCAS.2018.2833284}, ISSN={2156-3357}, month={Dec},}
H. R. Mahdiani, A. Ahmadi, S. M. Fakhraie, C. Lucas Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications IEEE Transactions on Circuits and Systems I: Regular Papers PDF Bibtex
@ARTICLE{5371902, author={H. R. {Mahdiani} and A. {Ahmadi} and S. M. {Fakhraie} and C. {Lucas}}, journal={IEEE Transactions on Circuits and Systems I: Regular Papers}, title={Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications}, year={2010}, volume={57}, number={4}, pages={850-862}, keywords={adders;digital arithmetic;fuzzy neural nets;VLSI;bio-inspired imprecise computational blocks;VLSI implementation;soft computing;digital hardware computational blocks;BIC adder;BIC multiplier;face recognition neural network;hardware defuzzification block;fuzzy processor;Very large scale integration;Costs;Neural networks;Uncertainty;Hardware;Face recognition;Fuzzy neural networks;Computer networks;Energy consumption;Network synthesis;Bio-inspired;face recognition;fuzzy processor;imprecise computational blocks;neural networks;very-large-scale integration}, doi={10.1109/TCSI.2009.2027626}, ISSN={1549-8328}, month={April},}
Ning Zhu, Wang Ling Goh, Kiat Seng Yeo An enhanced low-power high-speed Adder For Error-Tolerant application 2009 Proceedings of the 12th International Symposium on Integrated Circuits PDF Bibtex
@INPROCEEDINGS{5403865, author={ {Ning Zhu} and W. L. {Goh} and K. S. {Yeo}}, booktitle={Proceedings of the 2009 12th International Symposium on Integrated Circuits}, title={An enhanced low-power high-speed Adder For Error-Tolerant application}, year={2009}, volume={}, number={}, pages={69-72}, keywords={adders;integrated circuit design;VLSI;enhanced low-power high-speed adder;VLSI technology;test-error-tolerance;error-tolerant adder;power consumption;power delay product;Adders;Very large scale integration;Digital systems;Integrated circuit noise;Energy consumption;Power engineering and energy;Electronic mail;Degradation;Circuit testing;High speed integrated circuits;Adders;error-tolerance;high speed integrated circuits;low power design}, doi={}, ISSN={2325-0631}, month={Dec},}
Omid Akbari , Mehdi Kamal , Ali Afzali-Kusha , Massoud Pedram RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder IEEE Transactions on Circuits and Systems II: Express Briefs PDF Bibtex
@ARTICLE{7762134, author={O. {Akbari} and M. {Kamal} and A. {Afzali-Kusha} and M. {Pedram}}, journal={IEEE Transactions on Circuits and Systems II: Express Briefs}, title={RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder}, year={2018}, volume={65}, number={8}, pages={1089-1093}, keywords={adders;carry logic;energy conservation;MOSFET circuits;approximate operating modes;exact operating modes;RAP-CLA adder;error rate;FinFET technology;fast yet energy-efficient reconfigurable approximate carry look-ahead adder;size 15.0 nm;word length 32 bit;Adders;Delays;Power demand;Logic gates;Multiplexing;Error correction;Generators;Approximate computing;carry look-ahead adder (CLA);quality of service;reconfigurable}, doi={10.1109/TCSII.2016.2633307}, ISSN={1549-7747}, month={Aug},}
Fabio Frustaci , Stefania Perri , Pasquale Corsonello , Massimo Alioto Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation IEEE Transactions on Very Large Scale Integration (VLSI) Systems PDF Bibtex
@ARTICLE{8561219, author={F. {Frustaci} and S. {Perri} and P. {Corsonello} and M. {Alioto}}, journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, title={Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation}, year={2019}, volume={27}, number={4}, pages={964-968}, keywords={adders;energy consumption;power aware computing;energy reduction;ripple-carry adder;peak signal-to-noise ratio;energy-quality scalable adders;nonzeroing bit truncation;approximate addition;energy consumption;output quality;error-tolerant applications;innovative bit truncation strategy;quality degradation;truncation schemes;discrete cosine transform engine;silicon area overhead;noise figure 8.5 dB;Adders;Very large scale integration;Energy consumption;Art;Degradation;Discrete cosine transforms;Engines;Adaptive precision;approximate computing;energy-quality scaling;error-tolerant systems;low-power design;VLSI}, doi={10.1109/TVLSI.2018.2881326}, ISSN={1063-8210}, month={April},}
Darjn Esposito , Antonio Giuseppe Maria Strollo , Ettore Napoli , Davide De Caro , Nicola Petra Approximate Multipliers Based on New Approximate Compressors IEEE Transactions on Circuits and Systems I: Regular Papers PDF Bibtex
@ARTICLE{8383694, author={D. {Esposito} and A. G. M. {Strollo} and E. {Napoli} and D. {De Caro} and N. {Petra}}, journal={IEEE Transactions on Circuits and Systems I: Regular Papers}, title={Approximate Multipliers Based on New Approximate Compressors}, year={2018}, volume={65}, number={12}, pages={4169-4182}, keywords={approximation theory;filtering theory;image filtering;least mean squares methods;multiplying circuits;new approximate compressors;approximate computing;digital design;exact computation;power performance;efficient approximate multipliers;proposed circuits;image filtering;adaptive least mean squares filtering;Compressors;Logic gates;Error probability;Approximate computing;Approximation algorithms;Market research;Signal processing algorithms;Approximate computing;approximate multiplier;digital arithmetic}, doi={10.1109/TCSI.2018.2839266}, ISSN={1549-8328}, month={Dec},}
C. S. Wallace A Suggestion for a Fast Multiplier IEEE Transactions on Electronic Computers PDF Bibtex
@ARTICLE{4038071, author={C. S. {Wallace}}, journal={IEEE Transactions on Electronic Computers}, title={A Suggestion for a Fast Multiplier}, year={1964}, volume={EC-13}, number={1}, pages={14-17}, doi={10.1109/PGEC.1964.263830}}
C. R. Baugh , B. A. Wooley A Two's Complement Parallel Array Multiplication Algorithm IEEE Transactions on Computers PDF Bibtex
@ARTICLE{1672241, author={C. R. {Baugh} and B. A. {Wooley}}, journal={IEEE Transactions on Computers}, title={A Two's Complement Parallel Array Multiplication Algorithm}, year={1973}, volume={C-22}, number={12}, pages={1045-1047}, doi={10.1109/T-C.1973.223648}}
H. Jiang , C. Liu , F. Lombardi , J. Han Low-Power Approximate Unsigned Multipliers With Configurable Error Recovery IEEE Transactions on Circuits and Systems I: Regular Papers PDF Bibtex
@ARTICLE{8438521, author={H. {Jiang} and C. {Liu} and F. {Lombardi} and J. {Han}}, journal={IEEE Transactions on Circuits and Systems I: Regular Papers}, title={Low-Power Approximate Unsigned Multipliers With Configurable Error Recovery}, year={2019}, volume={66}, number={1}, pages={189-202}, doi={10.1109/TCSI.2018.2856245}}
A. B. Kahng , S. Kang Accuracy-configurable adder for approximate arithmetic designs DAC Design Automation Conference 2012 PDF Bibtex
@INPROCEEDINGS{6241600, author={A. B. {Kahng} and S. {Kang}}, booktitle={DAC Design Automation Conference 2012}, title={Accuracy-configurable adder for approximate arithmetic designs}, year={2012}, volume={}, number={}, pages={820-825}, doi={10.1145/2228360.2228509}}
D. Mohapatra , V. K. Chippa , A. Raghunathan , K. Roy Design of voltage-scalable meta-functions for approximate computing Design, Automation Test in Europe 2011 PDF Bibtex
@INPROCEEDINGS{5763154, author={D. {Mohapatra} and V. K. {Chippa} and A. {Raghunathan} and K. {Roy}}, booktitle={2011 Design, Automation Test in Europe}, title={Design of voltage-scalable meta-functions for approximate computing}, year={2011}, volume={}, number={}, pages={1-6}, doi={10.1109/DATE.2011.5763154}}