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Computing Units/Adders Add_OLOCA

Description:

Adders with and without ci, with and without co

Implementations:

There are: 8 implementations for this unit

Add_OLOCA

Version: v1

Reference paper:

  • Ayad Dalloo, Ardalan Najafi, Alberto Garcia-Ortiz Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder IEEE Transactions on Very Large Scale Integration (VLSI) Systems PDF Bibtex

                
    @ARTICLE{8341951, 
    author={A. {Dalloo} and A. {Najafi} and A. {Garcia-Ortiz}}, 
    journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, 
    title={Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder}, 
    year={2018}, 
    volume={26}, 
    number={8}, 
    pages={1595-1599}, 
    keywords={adders;cost reduction;logic design;logic gates;integrated systems;architectural template;hardware cost;systematic design;approximate adder;optimized lower part constant-OR adder;nonsystematic methodology;LOCA;time 10.0 year;word length 8 bit;Adders;Hardware;Logic gates;Computer architecture;Delays;Very large scale integration;Adder architecture;approximate computing;error-cost tradeoff;stochastic computing}, 
    doi={10.1109/TVLSI.2018.2822278}, 
    ISSN={1063-8210}, 
    month={Aug},}
                

  • Ardalan Najafi, Moritz Weissbrich, Guillermo Paya Vaya and Alberto Garcia-Ortiz A Fair Comparison of Adders in Stochastic Regime 2017 27th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) PDF Bibtex

                
    @INPROCEEDINGS{8106990, 
    author={A. {Najafi} and M. {Weissbrich} and G. {Paya-Vaya} and A. {Garcia-Ortiz}}, 
    booktitle={2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)}, 
    title={A fair comparison of adders in stochastic regime}, 
    year={2017}, 
    volume={}, 
    number={}, 
    pages={1-6}, 
    keywords={adders;logic design;low-power electronics;stochastic processes;error tolerant adder type II;power-efficient systems;approximate circuits;stochastic techniques;approximate arithmetic units;arithmetic circuits;adders;Adders;Computer architecture;Stochastic processes;Generators;Delays}, 
    doi={10.1109/PATMOS.2017.8106990}, 
    ISSN={}, 
    month={Sep.},}
                

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