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Computing Units/Template Adders Add_Hybrid

Description:

Template architectures which can be statically configured as different approximate adders

Implementations:

There are: 0 implementations for this unit

Add_Hybrid

Version: v1

Reference paper:

  • Ardalan Najafi, Moritz Weissbrich, Guillermo Paya Vaya and Alberto Garcia-Ortiz Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics IEEE Journal on Emerging and Selected Topics in Circuits and Systems PDF Bibtex

                
    @ARTICLE{8354693, 
    author={A. {Najafi} and M. {Weissbrich} and G. {Paya-Vaya} and A. {Garcia-Ortiz}}, 
    journal={IEEE Journal on Emerging and Selected Topics in Circuits and Systems}, 
    title={Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics}, 
    year={2018}, 
    volume={8}, 
    number={4}, 
    pages={736-745}, 
    keywords={adders;approximation theory;coherent design;hybrid approximate adders;unified design framework;technology scaling;nonsystematic methodology;robust error metrics;approximate accelerator;ad-hoc methodology;Adders;Error analysis;Systematics;Computer vision;Usability;Approximate adders;error metrics;computer vision;generic template;automatic design framework}, 
    doi={10.1109/JETCAS.2018.2833284}, 
    ISSN={2156-3357}, 
    month={Dec},}
                

  • Ardalan Najafi, Moritz Weissbrich, Guillermo Paya Vaya and Alberto Garcia-Ortiz A Fair Comparison of Adders in Stochastic Regime 2017 27th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) PDF Bibtex

                
    @INPROCEEDINGS{8106990, 
    author={A. {Najafi} and M. {Weissbrich} and G. {Paya-Vaya} and A. {Garcia-Ortiz}}, 
    booktitle={2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)}, 
    title={A fair comparison of adders in stochastic regime}, 
    year={2017}, 
    volume={}, 
    number={}, 
    pages={1-6}, 
    keywords={adders;logic design;low-power electronics;stochastic processes;error tolerant adder type II;power-efficient systems;approximate circuits;stochastic techniques;approximate arithmetic units;arithmetic circuits;adders;Adders;Computer architecture;Stochastic processes;Generators;Delays}, 
    doi={10.1109/PATMOS.2017.8106990}, 
    ISSN={}, 
    month={Sep.},}
                

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